february 2004 copyright ? alliance semiconduc tor. all rights reserved. as7c34096a 3.3v 512k 8 cmos sram ? 2/12/04, v. 1.2 alliance semiconductor p. 1 of 10 features ? pin compatible to as7c34096 ? industrial and commercial temperature ? organization: 524,288 words 8 bits ? center power and ground pins ? high speed - 10/12/15/20 ns address access time - 4/5/6/7 ns output enable access time ? low power consumption: active - 650 mw / max @ 10 ns ? low power consumption: standby - 18 mw / max cmos ? equal access and cycle times ? easy memory expansion with ce , oe inputs ? ttl-compatible, three-state i/o ? jedec standard packages - 400 mil 36-pin soj - 44-pin tsop 2 - 48 pin bga. 6 x 9mm ? esd protection 2000 volts ? latch-up current 200 ma logic block diagram 524,288 8 array (4,194,304) sense amp input buffer i/o8 i/o1 oe ce we column decoder row decoder control circuit a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd a8 a10 a11 a12 a13 a14 a15 a16 a17 a18 a9 pin arrangement s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 a15 oe i/o8 i/o7 gnd v cc i/o6 i/o5 a14 a13 a12 a11 a10 nc a0 a1 a2 a3 a4 ce i/o1 i/o2 v cc gnd i/o3 i/o4 we a5 a6 a7 17 18 a8 a9 36 35 34 33 nc a18 a17 a16 gnd v cc i/o6 i/o5 nc a14 a13 a12 a11 a10 a4 ce i/o1 i/o2 v cc gnd i/o3 i/o4 we a5 a6 a7 a8 a9 i/o8 i/o7 a1 a2 a3 a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a16 a15 a17 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 3 4 1 nc nc nc nc nc nc nc nc nc oe a18 36-pin soj (400 mil) 44-pin tsop 2 48-pin bga package 1 2 3 4 5 6 a a 0 a 1 nc a 3 a 6 a 8 b i/o 5 a 2 we a 4 a 7 i/o 1 c i/o 6 nc nc a 5 nc i/o 2 d v ss nc nc nc nc v cc e v cc nc nc nc nc v ss f i/o 7 nc a 18 a 17 nc i/o 3 g i/o 8 oe ce a 16 a 15 i/o 4 h a 9 a 10 a 11 a 12 a 13 a 14 selection guide ?10 ?12 ?15 ?20 unit maximum address access time 10 12 15 20 ns maximum outputenable access time 4 5 6 7 ns maximum operat ing current industrial 180 160 140 110 ma commercial 170 150 130 100 ma maximum cmos standby current 5 5 5 5 ma
? as7c34096a 2/12/04, v. 1.2 alliance semiconductor p. 2 of 10 functional description the as7c34096a is a high-performance cmos 4,194,304-bit static random access memory (sram) device organized as 524,288 words 8 bits. it is de signed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with output enable access times (t oe ) of 4/5/6/7 ns are ideal for high-performance applicat ions. the chip enable input ce permits easy memory expansion with multiple-bank memory systems. when ce is high the device enters standby mode. the device is gu aranteed not to exceed 18mw power consumption in cmos standby mode. a write cycle is accomplished by asserting write enable (we ) and chip enable (ce ). data on the input pins i/o1?i/o8 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and chip enable (ce ), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input addres s. when either chip enable or output enable is inactive, or wr ite enable is active, output drivers stay in high-impedance mode. all chip inputs and outputs are ttl-compatib le, and operation is from a single 3.3v s upply voltage. this device is available as per industry standard 400-mil 36-pin soj and 44-pin tsop 2 packages and also with 48 b ubga package with 6 x 9mm external dimension. note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational s ections of this spe cification is not implied. exposure to absolute maximum rating conditions for ex tended periods may affect reliability. key: x = don?t care, l = low, h = high absolute maximum ratings parameter symbol min max unit voltage on v cc relative to gnd v t1 ?0.5 +5.0 v voltage on any pin relative to gnd v t2 ?0.5 v cc +0.5 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 c temperature with v cc applied t bias ?55 +125 c dc current into output (low) i out ?20ma truth table ce we oe data mode h x x high z standby (i sb , i sb1 ) l h h high z output disable (i cc ) lhl d out read (i cc ) llx d in write (i cc )
? as7c34096a 2/12/04, v. 1.2 alliance semiconductor p. 3 of 10 * v il min = ?1.0v for pulse width less than 5ns. ** v ih max = v cc + 2.0v for pulse width less than 5ns. recommended operating condition parameter symbol min nominal max unit supply voltage v cc (10/12/15/20) 3.0 3.3 3.6 v input voltage v ih ** 2.0 ? v cc + 0.5 v v il * ?0.5 ? 0.8 v ambient operating temperature commercial t a 0? 70 c industrial t a ?40 ? 85 c dc operating characteristics (over the operating range ) 1 parameter symbol test conditions ?10 ?12 ?15 ?20 unit min max min max min max min max input leakage current |i li | v cc = max, v in = gnd to v cc ?1?1?1?1 a output leakage current |i lo | v cc = max, ce = v ih v out = gnd to v cc ?1?1?1?1 a operating power supply current i cc v cc = max, ce < v il f = f max , i out = 0ma industrial ?180?160?140?110ma commercial - 170 - 150 - 130 - 100 ma standby power supply current i sb v cc = max, ce = v ih f = f max , i out = 0ma ?60?60?60?60ma i sb1 v cc = max, ce v cc ? 0.2v, v in 0.2v or v in v cc ? 0.2v, f = 0 ?5?5?5?5ma output voltage v ol i ol = 8 ma, v cc = min ?0.4?0.4?0.4?0.4 v v oh i oh = ?4 ma, v cc = min 2.4?2.4?2.4?2.4? v c apacitance (f = 1mhz, t a = 25 c, v cc = nominal) 2 parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
? as7c34096a 2/12/04, v. 1.2 alliance semiconductor p. 4 of 10 key to switching waveforms read waveform 1 (address controlled) 3,6,7,9 read waveform 2 (ce , oe controlled) 3,6,8,9 read cycle (over the operating range) 3,9 parameter symbol ?10 ?12 ?15 ?20 unit notes min max min max min max min max read cycle time t rc 10?12?15?20?ns address access time t aa ?10?12?15?20ns3 chip enable (ce ) access time t ace ?10?12?15?20ns3 output enable (oe ) access time t oe ?4?5?6?7ns output hold from address change t oh 3?3?3?3?ns5 ce low to output in low z t clz 3?3?3?3?ns4, 5 ce high to output in high z t chz ?5?6?7?9ns4, 5 oe low to output in low z t olz 0?0?0?0?ns4, 5 oe high to output in high z t ohz ?5?6?7?9ns4, 5 power up time t pu 0?0?0?0?ns4, 5 power down time t pd ?10?12?15?20ns4, 5 undefined/don?t care falling input rising input address d out data valid t oh t aa t rc current supply oe d out t oe t olz t ace t chz t clz t pu t pd i cc i sb 50% 50% t ohz data valid t rc1 ce
? as7c34096a 2/12/04, v. 1.2 alliance semiconductor p. 5 of 10 write waveform 1 (we controlled) 10,11 write cycle (over the operating range) 11 parameter symbol ?10 ?12 ?15 ?20 unit notes min max min max min max min max write cycle time t wc 10?12?15?20?ns chip enable (ce ) to write end t cw 7 ? 8 ?10?12?ns address setup to write end t aw 7 ? 8 ?10?12?ns address setup time t as 0?0?0?0?ns write pulse width (oe = high) t wp1 7 ? 8 ?10?12?ns write pulse width (oe = low t wp2 10?12?15?20?ns address hold from end of write t ah 0?0?0?0?ns write recovery time t wr 0?0?0?0?ns data valid to write end t dw 5?6?7?9?ns data hold time t dh 0?0?0?0?ns4, 5 write enable to output in high z t wz 05060709ns4, 5 output active fr om write end t ow 3?3?3?3?ns4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t wr
? as7c34096a 2/12/04, v. 1.2 alliance semiconductor p. 6 of 10 write waveform 2 (ce controlled) 10,11 ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions . 4t clz and t chz are specified with c l = 5pf as in figure b. transition is m easured 500 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7ce and oe are low for read cycle. 8 address valid prior to or coincident with ce transition low. 9 all read cycle timings are referenc ed from the last valid address to the first transitioning address. 10 n/a 11 all write cycle timings are refere nced from the last valid address to the first transitioning address. 12 n/a 13 c=30pf, except on high z and low z parameters, where c=5pf. t aw address ce we d out t cw t wp t dw t dh t ah t wz t wc t as data valid d in t wr 350 ? c 13 320 ? d out gnd +3.3v figure b: 3.3v output load - output load: see figure b. - input pulse level: gnd to 3.0v. see figures a and b. - input rise and fall times: 2 ns. see figure a. - input and output timing reference levels: 1.5v. 168 ? thevenin equivalent: d out +1.728v 10% 90% 10% 90% gnd +3.0v figure a: input pulse 2 ns
? as7c34096a 2/12/04, v. 1.2 alliance semiconductor p. 7 of 10 package dimensions 44-pin tsop 2 min(mm) max(mm) a 1.2 a 1 0.05 0.15 a 2 0.95 1.05 b 0.30 0.45 c 0.12 0.21 d 18.31 18.52 e 1 10.06 10.26 e 11.68 11.94 e 0.80 (typical) l 0.40 0.60 36-pin soj 400 min(mils) max(mils) a 0.128 0.148 a 1 0.025 ? a 2 0.105 0.115 b 0.015 0.020 b 1 0.026 0.032 c 0.007 0.013 d .920 .930 e 0.045 0.055 e 0.370 bsc e 1 0.395 0.405 e 2 0.435 0.445 d e 1234567891011121314 44434241403938 37 36 35 34333231 15 16 30 29 17 1819 20 28 2726 25 c l a 1 a 2 e 44-pin tsop 2 0?5 21 24 23 e 1 a b seating plane 22 d pin 1 e e 1 e 2 a2 c a1 b b 1 a e 36-pin soj
? as7c34096a 2/12/04, v. 1.2 alliance semiconductor p. 8 of 10 48-ball fbga side view detail view e e2 e1 d die a e e2 0.3/typ y die ball #a1 top view ball #a1 index bottom view 1 2 3 4 5 6 a c d e f g h b a a b1 c1 sram die c elastomer b 48-ball fbga minimum typical maximum a ?0.75? b 5.90 6.00 6.10 b1 ?3.75? c 8.90 9.00 9.10 c1 ?5.25? d 0.30 0.35 0.40 e ? ? 1.20 e1 ?0.32? e2 0.24 0.27 0.3 y ? ? 0.10 notes 1. bump counts: 48 (8 row 6 column). 2. pitch: (x,y) = 0.75 mm 0.75 mm (typ). 3. units: millimeters. 4. all tolerance are 0.050 unless otherwise specified. 5. typ: typical. 6. y is coplanarity: 0.10 (max).
? as7c34096a 2/12/04, v. 1.2 alliance semiconductor p. 9 of 10 note: add suffix ?n? to the above part number for lead free parts. (ex: as7c34096a - 10 tin) ordering codes package temperature 10 ns 12 ns 15 ns 20 ns soj commercial as7c34096a-10jc as7c34096a-12jc as7c34096a-15jc as7c34096a-20jc industrial as7c34096a-10ji as7c34096a-12ji as7c34096a-15ji as7c34096a-20ji tsop 2 commercial as7c34096a-10tc as7c34096a -12tc as7c34096a-15tc as7c34096a-20tc industrial as7c34096a-10ti as7c34096a- 12ti as7c34096a-15ti as7c34096a-20ti bga commercial as7c34096a-10bc as7c34096a-12bc as7c34096a-15bc as7c34096a-20bc industrial as7c34096a-10bi as7c34096a-12bi as7c34096a-15bi AS7C34096A-20BI part numbering system as7c x 4096a ?xx j, t, or b x x sram prefix voltage: 3 - 3.3v cmos device number access time packages: j: soj 400 mil t: tsop 2 b: 48-ball fbga 6x9 mm temperature ranges: c: commercial, 0c to 70c i: industrial, ?40c to 85c n=lead free parts
alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel: 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved part number: as7c34096a document version: v. 1.2 ? copyright 2003 alliance semiconductor corp oration. all rights reserved. our three-po int logo, our name and intelliwatt are tr ademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of th eir respective companies. alliance reserve s the right to make changes to this document and its products at any time without notice. alliance assumes no respon sibility for any errors that ma y appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product desc ribed herein is under development, signifi cant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customer s and users, and is not intende d to operate as, or provide, any guarantee or warrantee to any user or cust omer. alliance does not assume any responsib ility or liability arising out of the app lication or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringe ment of any intellectual property rights, except as express ag reed to in alliance's terms and conditions of sale (which are available from alliance). all sa les of alliance products are made exclusively according to allian ce's terms and conditions of sale. the purchase of products from allianc e does not convey a license under any pate nt rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. allianc e does not authorize its products for use as critical compone nts in life-supporting systems where a malfunction or failure may reasonably be expected to resu lt in significant injury to the user, and the inclusion of all iance products in such life- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all clai ms arising from such use. as7c34096a ? ?
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